In recent years, for memory devices, miniaturization of process, increase of capacity and decrease in voltage have been promoted. This trend leads to a problem of increased rate of soft errors. Here, the soft errors are different from hard errors due to physical failures and the like disabling memory cells and are caused by environmental influences such as neutron rays. For the soft errors, memory devices become available by rewriting data.
In conventional memory devices, countermeasures have been taken against the soft errors such as error detection by redundancy and parity check or error correction by a majority decision circuit and an ECC circuit.
As a conventional art relating to the present invention, for example, Patent Document 1 described below is known. The semiconductor memory having an error correction function corrects errors of memory cells by using memory cell array units having odd numbers of three or more memory cells and majority decision circuits for each memory cell array unit.
Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 6-52697